(a) Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a MOS transistor and a method of manufacturing the same.
(b) Description of the Related Art
Generally, a Metal Oxide Silicon (MOS) transistor has a gate insulating layer formed on a semiconductor substrate, a gate formed on the insulating layer, and source and drain regions formed within the substrate on both sides of the gate. Various manufacturing methods of this transistor are disclosed in U.S. Pat. Nos. 6,635,924, 6,548,856, 5,940,707, 5,888,868, and 5,719,067.
A conventional MOS transistor will be described with reference to FIG. 1.
As shown in FIG. 1, a gate insulating layer 11 and a gate 12 of a polysilicon are sequentially formed on a semiconductor substrate 10, and lightly doped drain (LDD) regions 13a and 13b being formed of low concentration impurities are formed within the substrate 10 on both sides of the gate 12. A spacer 14 is formed on the sidewall of the gate 12, and source and drain regions 15a and 15b being formed of high concentration impurities are formed within the substrate 10 on both sides of the spacer 14.
In this MOS transistor, in the case a voltage of more than a threshold voltage is applied to the gate 12, charge carriers flow from the source region 15a to the drain region 15b, so that a channel is horizontally formed within the substrate 10 below the gate 12.
Recently, for the purpose of achieving a high integration density device, the channel length below the gate 12 has been decreased, and the source and drain regions 15a and 15b have been formed with shallow junctions, so as to prevent a short channel effect due to the decrease of the channel length.
However, in the conventional MOS transistor as described above, if the channel length decreases to for example nano size, there is a problem in that it is difficult to form an ultra fine gate of the nano size and source and drain region of the shallow junctions by conventional manufacturing processes due to photolithography limitations.
Accordingly, to form the ultra fine gate and source and drain region of the shallow junctions, new pattern techniques, such as electron beam and X line exposure methods must be applied to fabricating the MOS transistor, but it is impossible to mass-produce ultra fine devices using these techniques, as these techniques are not fully established.
Furthermore, for the purpose of achieving a high integration density device, devices of novel structures have been developed, but it is difficult to fabricate these devices.